library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SUMA_ANGLE is 
	port( I1 			 : in std_logic_vector(28 downto 0); --El que es +- deltafi
		   I2			 :	in std_logic_vector(28 downto 0); --El que se realimenta, comprendido entre -180 y 180
		   O			 : out std_logic_vector(28 downto 0)
	);
end SUMA_ANGLE;

architecture suma of SUMA_ANGLE is
begin
	process(I1,I2)
	    variable output: std_logic_vector(28 downto 0);
	begin
	    output := I1 + I2;
	    if (output(28)='0') and (output>std_logic_vector(to_signed(89999999,29))) then
	        O <= std_logic_vector(to_signed(89999999,29));
	    elsif (output(28)='1') and (output<std_logic_vector(to_signed(-89999999,29))) then
	        O <= std_logic_vector(to_signed(-89999999,29));
	    else
	        O <= output;
	    end if;
	end process;
end suma;


--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;

--entity test_sum is
--end test_sum;

--architecture simul2 of test_sum is
--	component SUMA_ANGLE is
--	port( I1 			 : in std_logic_vector(28 downto 0); --El que es +- deltafi
--		   I2			 :	in std_logic_vector(28 downto 0); --El que se realimenta, comprendido entre -180 y 180
--		   O			 : out std_logic_vector(28 downto 0)
--	);
--	end component;

--	signal In1 : std_logic_vector (28 downto 0):=std_logic_vector(to_signed(-703125,29));
--	signal In2 : std_logic_vector (28 downto 0):=std_logic_vector(to_signed(-179999000,29));
--	signal output : std_logic_vector (28 downto 0);
	
	
--begin
    
--	sum : SUMA_ANGLE port map (In1,In2,output);
	


--end simul2;